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Three‐dimensional AND flash memory

Published:2017-05 Issue:11 Volume:53 Page:739-741
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Kim Y.¹,Park I.H.²,Kwon H.T.¹,Wee D.¹,Park B.‐G.³

Affiliation:

1. Department of Nanoenergy Engineering, BK21 Plus Nanoconvergence Technology DivisionPusan National UniversityBusanKorea

2. Flash Design TeamSamsung ElectronicsHwasungKorea

3. Department of Electrical and Computer EngineeringSeoul National UniversitySeoulKorea

Funder

Pusan National University

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2017.0465

Reference6 articles.

1. Kim K.: ‘Silicon technologies and solutions for the data‐driven world’.IEEE ISSCC Dig. Tech. Papers 2015 pp.8–14 https://doi/org/10.1109/ISSCC.2015.7062845

2. Three‐dimensional NAND flash architecture design based on single‐crystalline stacked array;Kim Y.;IEEE Trans. Electron Devices,2012

3. Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

4. A 128 Gb 3b/cell V‐NAND flash memory with 1 Gb/s I/O rate;Jeong W.;IEEE J. Solid‐State Circuits,2016

5. A subthreshold slope and low‐frequency noise characteristics in charge trap flash memories with gate‐all‐around and planar structure;Lee M.‐S.;IEEE J. Semicond. Technol. Sci.,2012

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. On-chip adaptive matching learning with charge-trap synapse device and ReLU activation circuit;Solid-State Electronics;2021-12

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