Two‐dimensional sorting algorithm for high‐throughput K‐best MIMO detection
Author:
Affiliation:
1. 5500 Campanile Dr. MC 1309, San Diego State UniversitySan Diego92182USA
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-com.2016.0790
Reference16 articles.
1. WenkM. ZellwegerM. BurgA.et al.: ‘K‐best MIMO detection VLSI architectures achieving up to 424 Mbps’. Proc. IEEE Int. Symp. Circuits Syst. 2006 pp.1151–1154
2. Relaxed $K$-Best MIMO Signal Detector Design and VLSI Implementation
3. A 675 Mbps, 4 $\times$ 4 64-QAM K-Best MIMO Detector in 0.13 $\mu{\rm m}$ CMOS
4. Small‐area and low‐energy K‐best MIMO detector using relaxed tree expansion and early forwarding;Kim T.‐H.;IEEE Trans. Circuits Syst. I,2010
5. HeidmannN. WiegandT. PaulS.: ‘Architecture and FPGA‐implementation of a high throughput K+ best detector’. Automation and Test in Europe Conf. and Exhibition 2011 pp.1–6
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