State minimisation-based loop handling for critical path analysis-Reference-Cited by-同舟云学术

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State minimisation-based loop handling for critical path analysis

Published:1996 Issue:1 Volume:32 Page:8
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. Lett.

Author:

Han S.Y.,Kim Y.H.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/el_19960021?crawler=true&mimetype=application/pdf

Reference7 articles.

1. Timing Analysis and Performance Improvement of MOS VLSI Designs

2. A Switch-Level Timing Verifier for Digital MOS VLSI

3. Kim, Y.H.: ‘Accurate timing verification for digital VLSI designs’. Memo. No. UCB/ERL M89/2, University of California, Berkeley, Jan. 1989

4. Automating the design of asynchronous sequential logic circuits

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