Low-power circuit implementation for partial-product addition using pass-transistor logic
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/ip-cds_19990328?crawler=true&mimetype=application/pdf
Reference14 articles.
1. Low-power CMOS digital design
2. A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer
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