Hardware implementation of a pulse-stream neural network

Author:

Haycock R.J.,York T.A.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Reference17 articles.

1. Rumelhart, D.E., and McCelland, J.L.: ‘Parallel distributed processing, explorations in the microstructure of cognition — volume 1: foundations’, (The Massachusetts Institute of Technology London 1986)

2. Aleksander, I., and Morton, H.: ‘An introduction to neural computing’, (Chapman and Hall London 1991)

3. Murray, A.F., and Tarassenko, L.: ‘Analogue neural VLSI, a pulse stream approach’, (Chapman and Hall London 1994)

4. Glesner, M., and Pochmuller, W.: ‘Neurocomputers, an overview of neural networks in VLSI’, (Chapman and Hall London 1994)

5. Kung, S.Y.: ‘Digital neural networks’, (PTR Prentice-Hall Englewood Cliffs 1993)

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1. Synchronization: a tool for validating a PWL circuit that approximates the Hindmarsh-Rose neuron model;Nonlinear Theory and Its Applications, IEICE;2012

2. An approach for transistor implementation of neural networks and its various prospects and limitations;2010 The 2nd International Conference on Computer and Automation Engineering (ICCAE);2010-02

3. Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation;SPIE Proceedings;2004-05-28

4. CMOS PWM VLSI implementation of neural network;Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium;2000

5. Using pulsed activation to design a wide dynamic range PWM neuron circuit;ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

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