Affiliation:
1. Department of Electronics & Communication Engineering National Institute of Technology Warangal India
2. Department of Electrical Engineering Indian Institute of Technology Ropar Rupnagar India
Abstract
AbstractFor the first time, a physics‐based modelling of a nanoscale Ni/Mo/MoO3/Ni memristor is presented in this letter by inserting a ‘Mo:Capping layer’ between the top electrode (Ni) and the insulating layer (MoO3). The proposed memristor has stable hysteresis I–V characteristics as well as a significant reduction in ‘Forming voltage’ (VFORM) to 0.75 V. The simulated resistive switching responses using the COMSOL Multiphysics package demonstrate consistently low values of coefficient of variability (CV) with 14.31% and 14.85% for the SET and RESET modules, respectively, during cycle‐to‐cycle variations along with a low compliance current (ICC) of 193 µA. In addition to observing synaptic plasticity behaviour, it also examines how ramp‐rates impact ‘Potentiation’ and ‘Depression’ as memristor conductance (G) is closely related to synaptic weights.
Publisher
Institution of Engineering and Technology (IET)
Cited by
1 articles.
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