An Parallel FPGA SAT Solver Based on Multi‐Thread and Pipeline

Author:

Tiejun LI1,Kefan MA1,Jianmin ZHANG1

Affiliation:

1. College of Computer, National University of Defense TechnologyChangsha410073China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Applied Mathematics,Electrical and Electronic Engineering

Reference29 articles.

1. SAT and SMT Solvers: A foundational perspective;Ganesh V;Engineering Secure and Dependable Software Systems,2019

2. HülleR FierPandSchmidtJ “PBO‐based fault selection for compact test generation” 7th Prague Embedded Systems Workshop https://pesw.fit.cvut.cz/2019/index.php?page=Program 2019‐6‐27

3. SAT‐based equivalence checking of threshold logic designs for nanotechnologies;Zheng Y;Proceedings of the 18th ACM Great Lakes Symposium on VLSI,2008

4. Attacking Bivium using SAT solvers;Eibach T;International Conference on Theory and Applications of Satisfiability Testing,2008

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