Analysis on Three‐Dimensional Gate Edge Roughness of Gate‐All‐Around Devices
Author:
Affiliation:
1. Department of Micro‐NanoelectronicsPeking UniversityBeijing100871China
2. Beijing Laboratory of Future IC Technology and SciencePeking UniversityBeijing100871China
Funder
National Key Research and Development Program of China
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Applied Mathematics,Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/cje.2021.06.008
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