Dynamic scheduling of tasks on partially reconfigurable FPGAs-Reference-Cited by-同舟云学术

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Dynamic scheduling of tasks on partially reconfigurable FPGAs

Published:2000 Issue:3 Volume:147 Page:181
ISSN:1350-2387
Container-title:IEE Proceedings - Computers and Digital Techniques
language:en
Short-container-title:IEE Proc., Comput. Digit. Tech.

Author:

Diessel O.,ElGindy H.,Middendorf M.,Schmeck H.,Schmidt B.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science

Link

https://digital-library.theiet.org/content/journals/10.1049/ip-cdt_20000485?crawler=true&mimetype=application/pdf

Reference14 articles.

1. WIRTHLIN, M.J., and HUTCHINGS, B.L.: ‘Sequencing run-time reconfigured hardware with software’,ACM Fourth International Symposium on Field Programmable Gate Arrays(FPGA'96), (ACM Press, New York 1996), p. 122–128

2. EGGERS, H., LYSAGHT, P., DICK, H., and MCGREGOR, G.: ‘Fast reconfigurable crossbar switching in FPGAs’, HARTENSTEIN, R.W., GLESNER, M., Proceedings of 6th International Workshop onField-Programmable Logic(FPL'96) LNCS 1142, (Springer-Verlag, Berlin, Germany 1996), p. 297–306

3. Programmable active memories: reconfigurable systems come of age

4. Video communications using rapidly reconfigurable hardware

5. ELDREDGE, J.G., and HUTCHINGS, B.L.: ‘Density enhancement of a neural network-using FPGAs and run-time reconfiguration’, BUELL, D.A., POCEK, K.L., Proceedings of IEEE Workshop onFPGAs for custom computing machines, (IEEE Computer Society, Los Alamitos, CA 1994), p. 180–188

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