Bottom-up approach in automated embedded memory model generation for high-performance microprocessors

Author:

Bhadra J.,Abadir M.S.,Burgess D.,Trofimova E.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science

Reference24 articles.

1. Motorola Inc.: ‘e500 core complex reference manual’, 2003

2. ‘Speedier “Book E” Encore’, Microprocessor report, 2001

3. Pyron, C.,et al.: ‘DFT advances in Motorola's MPC7400, a PowerPC Microprocessor’. Int. Test. Conf., ITC, 1999

4. Pyron, C., Prado, J., and Golab, J.: ‘Test strategies for the PowerPC 750 microprocessor’,IEEE Des. Test Comput., 1998,15, pp. 90–97

5. Pyron, C., Bangalore, R., Belete, D., Goertz, J., Razdan, A., and Younger, D.: ‘Silicon symptoms to solutions: applying design for debug techniques’. Int. Test Conf., ITC, 2002

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