Efficient approach to synthesis of multioutput boolean functions on PAL-based devices

Author:

Kania D.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science

Reference14 articles.

1. Sharma, K.: ‘Programmable Logic Handbook, PLDs, CPLDs, & FPGAs’, 1st(McGraw-Hill, New York 1988)

2. Brayton, R.K., Hachtel, G.D., McMullen, C., and Sangiovanni-Vincentelli, A.L.: ‘Logic minimization algorithms for VLSI synthesis’, 1st(Kluwer Academic Publishers, Boston 1984)

3. De Micheli, G.: ‘Synthesis and optimization of digital circuits’, 1st(McGraw-Hill International, USA 1984)

4. Two-level logic synthesis on PALs

5. Multi-level synthesis on PALs

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