Decoding of CISC instructions in superscalar processors with high issue rate-Reference-Cited by-同舟云学术

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Decoding of CISC instructions in superscalar processors with high issue rate

Published:2000 Issue:2 Volume:147 Page:101
ISSN:1350-2387
Container-title:IEE Proceedings - Computers and Digital Techniques
language:en
Short-container-title:IEE Proc., Comput. Digit. Tech.

Author:

Shiu R.-M.,Chiu J.-C.,Cheng S.-K.,Shann J.J.-J.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science

Link

https://digital-library.theiet.org/content/journals/10.1049/ip-cdt_20000450?crawler=true&mimetype=application/pdf

Reference16 articles.

1. ‘INTEL. `Pentium II processor family developer's manual’, Oct. 1997

2. LINDHOLM, T., and YELLIN, F.: The Java virtual machine specification, (Addison-Wesley 1997)

3. JOHNSON, M.: Superscalar microprocessor design, (Prentice Hall 1991)

4. SHRIVER, B., and SMITH, B.: The anatomy of a high-performance microprocessor: A systems perspective, (IEEE Computer Society Press 1998)

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-bandwidth x86 instruction fetching based on instruction pointer table;IEE Proceedings - Computers and Digital Techniques;2001-05-01

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