Reed--Muller tree-based minimisation of fixed polarity Reed–Muller expansions
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science
Link
https://digital-library.theiet.org/content/journals/10.1049/ip-cdt_20010252?crawler=true&mimetype=application/pdf
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1. Easily Testable Realizations ror Logic Functions
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5. On the complexity of mod-2l sum PLA's
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2. Area minimization of MPRM circuits;2009 IEEE 8th International Conference on ASIC;2009-10
3. Compact representations of logic functions for lossless compression of grey-scale images;IEE Proceedings - Computers and Digital Techniques;2004
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