Analytical approach to sizing nFET chains-Reference-Cited by-同舟云学术

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Analytical approach to sizing nFET chains

Published:1992 Issue:14 Volume:28 Page:1334
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. Lett.

Author:

Bizzan S.S.,Jullien G.A.,Miller W.C.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/el_19920847?crawler=true&mimetype=application/pdf

Reference9 articles.

1. Bizzan, S.: ‘High performance VLSI circuit techniques’, 1991, MASc Thesis, University of Windsor p. 30–39

2. Canadian Microelectronics Corporation: Guide to the Integrated Circuit Implementation Services of the Canadian Microelectronics Corporation 1986

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. On optimal tapering of FET chains in high-speed CMOS circuits;IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;2001

2. Modeling the transistor chain operation in CMOS gates for short channel devices;IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications;1999

3. A parallel back-propagation adder structure;International Journal of Electronics;1998-09

4. Collapsing the CMOS transistor chain to an effective single equivalent transistor;IEE Proceedings - Circuits, Devices and Systems;1998

5. Fast adders using enhanced multiple-output domino logic;IEEE Journal of Solid-State Circuits;1997

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