High speed, open loop residue amplifier with linearity improvement

Author:

Pirbazari Mahmoud Mahdipour1,Hadidi Khayrollah1,Khoei Abdollah1,Sadrafshari Shamim1

Affiliation:

1. Microelectronics Research LaboratoryUrmia UniversityUrmiaIran

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Reference26 articles.

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2. Bucher M. Diles G. Makris N.: ‘Analog performance of advanced CMOS in weak moderate and strong inversion’.Proc. 17th Int. Conf. Mixed Design of Integrated Circuits and System. (MIXDES) 2010 pp.54–57

3. A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers

4. A 4 Gsample/s 8b ADC in 0.35 um CMOS;Poulton K.;IEEE ISSCC Tech. Dig.,2002

5. Poulton K. Neff R. Setterberg B. et al.: ‘A 20 GS/s 8b ADC with a 1 MB memory in 0.18 um CMOS’ IEEE ISSCC Tech. Dig. 2003 pp.318–496

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1. Design of high speed 2-stage OTA for high capacitive load of 120 pF and 2.96 V;Engineering Research Express;2021-12-01

2. A new fast settling low power CMOS gain stage architecture;Analog Integrated Circuits and Signal Processing;2016-09-26

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