Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity-Reference-Cited by-同舟云学术

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Self‐gated resonant‐clocked flip‐flop optimised for power efficiency and signal integrity

Published:2016-03 Issue:2 Volume:10 Page:94-103
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Dominic Jawahar Jennifer Judy¹,Mysore Shivananda Murthy Supreeth¹,Vettuvanam Somasundaram Kanchana Bhaaskaran¹

Affiliation:

1. School of Electronics EngineeringVIT UniversityChennaiIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2014.0282

Reference30 articles.

1. A low power sinusoidal clock;Voss B.;Proc. IEEE Int. Symp. Circuits and Systems,2001

2. Low-power digital systems based on adiabatic-switching principles

3. Resonant-Clock Latch-Based Design

4. Energy-Efficient GHz-Class Charge-Recovery Logic

5. A low-power microprocessor based on resonant energy

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1. Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures;Journal of Circuits, Systems and Computers;2019-04-23

2. Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL);Journal of Circuits, Systems and Computers;2017-12-06

3. A novel PDWC-UCO algorithm-based buffer placement in FPGA architecture;International Journal of Circuit Theory and Applications;2016-10-24

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