Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits
Author:
Affiliation:
1. Department of Computer EngineeringShahid Bahonar University of KermanKermanIran
2. School of Electrical & Computer EngineeringShiraz UniversityShirazIran
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2018.5616
Reference37 articles.
1. Circuit reliability
2. Parameter variations and impact on circuits and microarchitecture
3. Statistical static timing analysis: A survey
4. Statistical Timing Analysis: From Basic Principles to State of the Art
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