Concurrent error detection in semi-systolic dual basis multiplier over GF(2m) using self-checking alternating logic-Reference-Cited by-同舟云学术

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Concurrent error detection in semi-systolic dual basis multiplier over GF(2m) using self-checking alternating logic

Published:2010 Issue:5 Volume:4 Page:382
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits Devices Syst.

Author:

Chiou C.W.,Liang W.-Y.,Chang H.W.,Lin J.-M.,Lee C.-Y.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2009.0243?crawler=true&mimetype=application/pdf

Reference56 articles.

1. Macwilliams, F.J., and Sloane, N.J.A.: ‘The theory of error-correcting codes’, (North-Holland, Amsterdam 1977)

2. Blahut, R.E.: ‘Fast algorithms for digital signal processing’, (Addison-Wesley, Reading, MA 1985)

3. The use of finite fields to compute convolutions

4. Bit-serial Reed - Solomon encoders

5. Efficient bit-serial multiplication and the discrete-time Wiener-Hopf equation over finite fields

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1. Dickson basis multiplier with concurrent error detection against fault attacks for lightweight cryptosystems;Electronics Letters;2022-04-17

2. Review of gate‐level differential power analysis and fault analysis countermeasures;IET Information Security;2014-01

3. Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m);Journal of Signal Processing Systems;2013-06-11

4. Concurrent All-Cell Error Detection in Semi-Systolic Multiplier Using Linear Codes;Applied Mathematics & Information Sciences;2013-05-01

5. Full Multiplexers Implementation of Dual Basis Multiplier over GF(2^m);Applied Mechanics and Materials;2013-01

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