Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits-Reference-Cited by-同舟云学术

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

Published:2013-09 Issue:5 Volume:7 Page:273-282
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Chen Xiaoming¹,Luo Hong¹,Wang Yu¹,Cao Yu²,Xie Yuan³,Ma Yuchun⁴,Yang Huazhong¹

Affiliation:

1. Department of Electronic EngineeringTsinghua National Laboratory for Information Science and TechnologyTsinghua UniversityBeijing100084People's Republic of China

2. Department of ECEEArizona State UniversityTempeArizona85287‐5706USA

3. Department of CSEPennsylvania State UniversityPennsylvania16802USA

4. Department of Computer ScienceTsinghua National Laboratory for Information Science and TechnologyTsinghua UniversityBeijing100084People's Republic of China

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2012.0361

Reference26 articles.

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4. Luo H. Wang Y. Cao Y. Xie Y. Ma Y. Yang H.: ‘Temporal performance degradation under RTN: evaluation and mitigation for nanoscale circuits’.IEEE Computer Society Annual Symp. VLSI (ISVLSI) August2012 pp.183–188

5. Tega N. Miki H. Ren Z. et al.: ‘Reduction of random telegraph noise in high‐k/metal‐gate stacks for 22 nm generation FETs’.IEEE Int. Electron Devices Meeting (IEDM) December2009 pp.1–4