Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism-Reference-Cited by-同舟云学术

Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism

Published:2010 Issue:2 Volume:4 Page:147
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits Devices Syst.

Author:

Lee J.-Y.,Lee J.-J.,Park S.M.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2009.0038?crawler=true&mimetype=application/pdf

Reference14 articles.

1. ‘Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec.H.264 jISO/IEC 14496-10AVC),’ in Joint Video Team, March 2003, Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050

2. ‘VC-1 Compressed Video Bitstream Format and Decoding Process (SMPTE 421M-2006)’, SMPTE Standard, 2006

3. Mapping of H.264 decoding on a multiprocessor architecture

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