All‐digital delay line‐based time difference amplifier in 65 nm CMOS technology-Reference-Cited by-同舟云学术

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All‐digital delay line‐based time difference amplifier in 65 nm CMOS technology

Published:2019-04-30 Issue:4 Volume:13 Page:421-427
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Razmdideh Ramin¹,Saneei Mohsen¹

Affiliation:

1. Department of Electrical EngineeringShahid Bahonar University of Kerman22 Bahman BlvdKermanIran

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2018.5304

Reference26 articles.

1. A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC

2. A 450 fs 65‐nm CMOS millimeter‐wavetime‐to‐digital converter using statistical element selection for all‐digital PLLs;Hussein A.I.;IEEE J. Solid‐State Circuits,2017

3. A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology

4. Two-Dimensions Vernier Time-to-Digital Converter

5. A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques

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