Fault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology
Author:
Affiliation:
1. VLSI & Dependable System Design Lab, Electrical Engineering DepartmentShahid Bahonar University of KermanKerman76169133Iran
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2017.0380
Reference20 articles.
1. Simulation of SET faults in a voltage controlled oscillator
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4. Reliability analysis of static and dynamic fault‐tolerant systems subject to probabilistic common‐cause failures;Xing L.;J. Risk Reliab.,2009
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