A Self‐Biased Low‐Jitter Process‐Insensitive Phase‐Locked Loop for 1.25Gb/s‐6.25Gb/s SerDes
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Published:2018-09
Issue:5
Volume:27
Page:1009-1014
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ISSN:1022-4653
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Container-title:Chinese Journal of Electronics
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language:en
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Short-container-title:Chin. j. electron.
Author:
YUAN Hengzhou1,
GUO Yang1,
LIU Yao1,
LIANG Bin1,
GUO Qiancheng1
Affiliation:
1. College of Computer ScienceNational University of Defense TechnologyChangsha410073China
Funder
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Applied Mathematics,Electrical and Electronic Engineering