Integer codes correcting single errors and detecting burst errors within two bytes

Author:

Radonjic Aleksandar1ORCID,Ristic Igor2,Scepanovic Ivan2

Affiliation:

1. Institute of Technical Sciences of the Serbian Academy of Sciences and Arts Belgrade Serbia

2. Department of Informatics University Union Nikola Tesla Sremski Karlovci Serbia

Abstract

AbstractThe need for fast communication has led to the introduction of 100 Gbps optics in local area networks (LANs). To avoid retransmission of corrupted packets, in some LANs, the CRC codes were replaced by Reed‐Solomon (RS) codes. Although this solution has met its primary goal, it has two drawbacks: first, the payload size was significantly reduced, and second, each network node had to be equipped with much more complex hardware, which increased the cost of the network. Starting from the fact that the vast majority of corrupted packets contain only single errors, in this paper, a simple strategy for error control in 100 Gbps optical LANs is presented. More precisely, instead of protecting the data with the CRC or RS codes, using integer codes is suggested that can correct single errors and detect two types of burst errors: l‐bit burst errors within one b‐bit byte and h‐bit burst errors within two b‐bit bytes (1 ≤ h < l < b). Unlike the CRC or RS codes, the proposed ones use integer and lookup table operations, which are supported by all processors. In addition, the proposed codes can be interleaved without delay and without using any additional hardware. This feature allows the decoder not only to process larger data sets in parallel, but also to detect all double burst errors.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference19 articles.

1. James L. Moore A. Glick M. Bulpin J.:Physical layer impact upon packet errors. In:Proceedings of Passive and Active Measurement Workshop (PAM 2006) pp.1–10. Springer Cham (2006)

2. Sobe P.:Parallel reed‐solomon coding on multicore processors. In:Proceedings of International Workshop Storage Network Architecture and Parallel I/Os pp.71–80. IEEE Piscataway (2010)

3. A Processor Accelerator for Software Decoding of Reed-Solomon Codes

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