Security and fault tolerance evaluation of TMR–QDI circuits-Reference-Cited by-同舟云学术

Security and fault tolerance evaluation of TMR–QDI circuits

Published:2019-05 Issue:3 Volume:13 Page:213-222
ISSN:1751-8717
Container-title:IET Information Security
language:en
Short-container-title:IET Information Security

Author:

Ait Abdelmalek Ghania¹,Ziani Rezki¹,Mokdad Rabah²

Affiliation:

1. Department of ElectronicsMouloud Mammeri UniversityTizi OuzouAlgeria

2. Department of PhysicsMouloud Mammeri UniversityTizi OuzouAlgeria

Publisher

Institution of Engineering and Technology (IET)

Subject

Computer Networks and Communications,Information Systems,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-ifs.2018.5439

Reference50 articles.

1. Biham E. Shamir A.: ‘Differential fault analysis of secret key cryptosystems’.Proc. Int. Conf. on Advances in Cryptology (CRYPTO) Santa Barbara California USA August1997 pp.513–525

2. Fast and automatic security test on cryptographic ICs against fault injection attacks based on design for security test;Cuiping S.;IET Inf. Sec.,2017

3. Kocher P.C.: ‘Timing attacks on implementations of Diffie–Hellman RSA DSS and other systems’.Proc. Int. Conf. on Advances in Cryptology (CRYPTO) Santa Barbara California USA August1996 pp.104–113

4. Quisquater J.J. Samyde D.: ‘Electromagnetic analysis (EMA): measures and countermeasures for smart cards’.Proc. Int. Conf. on Research in Smart Cards Cannes France September2001 pp.200–201

5. Tiri K. Verbauwhede I.: ‘A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation’.Proc. Int. Conf. on Design Automation and Test in Europe. (DATE) Paris France February2004 pp.246–251

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1. Slow Slopes for Optimizing the Fault Detection in Secure QDI Circuits;Lecture Notes in Networks and Systems;2023

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