On‐chip generation of primary input sequences for multicycle functional broadside tests

Author:

Pomeranz Irith1

Affiliation:

1. School of ECEPurdue University465 Northwestern AvenueWest LafayetteIN47907USA

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference22 articles.

1. Rearick J.: ‘Too much delay fault coverage is a bad thing’.Proc. Int. Test Conf. 2001 pp.624–633

2. Saxena J. Butler K.M. Jayaram V.B. et al.: ‘A case study of IR‐drop in structured at‐speed testing’.Proc. Int. Test Conf. 2003 pp.1098–1104

3. Sde‐Paz S. Salomon E.: ‘Frequency and power correlation between at‐speed scan and functional tests’.Proc. Int. Test Conf. 2008 Paper 13.3 pp.1–9

4. Generation of functional broadside tests for transition faults;Pomeranz I.;IEEE Trans. Comput.‐Aided Des.,2006

5. Valka M. Bosio A. Dilillo L. et al.: ‘A functional power evaluation flow for defining test power limits during at‐speed delay testing’.Proc. IEEE European Test Symp. 2011 pp.153–158

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