High throughput fault‐resilient AES architecture-Reference-Cited by-同舟云学术

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High throughput fault‐resilient AES architecture

Published:2019-03-05 Issue:4 Volume:13 Page:312-323
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Sheikhpour Saeide¹,Mahani Ali¹,Bagheri Nasour²³

Affiliation:

1. Department of Electrical EngineeringShahid Bahonar UniversityKermanIran

2. Department of Electrical EngineeringShahid Rajaee Teacher Training UniversityTehranIran

3. School of Computer ScienceInstitute for Research in Fundamental Sciences (IPM)TehranIran

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.5083

Reference20 articles.

1. Daemen J. Rijmen V.: ‘AES proposal: Rijndael’ AES algorithm submission 1999

2. National Institute of Standards and Technology (NIST): ‘Advanced encryption standard (AES)’ FIPS Publication 197

3. Kocher P.C.: ‘Timing attacks on implementations of Diffie‐Hellman RSA DSS and other systems’.Advances in Cryptology CRYPTO Santa Barbara CA USA 1996(LNCS 1109) pp.104–113

4. Kocher P.C. Jaffe J. Jun B.: ‘Differential power analysis’.Advances in Cryptology CRYPTO Santa Barbara CA USA 1999(LNCS 1666) pp.388–397

5. Gandolfi K. Mourtel C. Oliver F.: ‘Electromagnetic analysis: concrete results’.Proc. Cryptographic Hardware and Embedded Systems: CHES 2001 Paris France 2001 pp.251–261

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient AES 32-Bit Architecture Resistant to Fault Attacks;Computers, Materials & Continua;2022

2. A low cost fault-attack resilient AES for IoT applications;Microelectronics Reliability;2021-08

3. Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme;IET Computers & Digital Techniques;2021-05-17

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