Yield modelling and analysis of bundled data and ring‐oscillator based designs

Author:

Zhang Yang1ORCID,Li Ji1ORCID,Cheng Huimei1,Zha Haipeng1,Draper Jeffrey1,Beerel Peter A.1

Affiliation:

1. University of Southern CaliforniaLos AngelesUSA

Funder

National Science Foundation

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference25 articles.

1. PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

2. Micropipelines

3. Russell G. Yakovlev A. Bystrov A. et al.: ‘On‐chip structures for timing measurements and test’.Proc. of the 8th Int. Symp. on Asynchronus Circuits and Systems. IEEE Computer Society 2002 p.190

4. A Designer's Guide to Asynchronous VLSI

5. Petlin O.A. Furber S.B.: ‘Scan testing of micropipelines’.Proc. of the 13th IEEE VLSI Test Symp. 1995 pp.296–301

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