Probabilistic timing analysis of time‐randomised caches with fault detection mechanisms
Author:
Affiliation:
1. School of Information Science and TechnologyZhejiang Sci‐Tech UniversityZhejiangPeople's Republic of China
2. Ecole Polytechnique de MontrealMontrealH3T 1J4Canada
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.5043
Reference30 articles.
1. Bernat G. Petters S.: ‘WCET analysis of probabilistic hard real‐time systems’.23rd IEEE Real‐Time Systems Symp. (RTSS 2002) Austin TX USA 2002 pp.279–288
2. Smith J.E. Goodman J.R.: ‘A study of instruction cache organizations and replacement policies’.Proc. 10th Annual Int. Symp. on Computer Architecture (ISCA'83) Stockholm Sweden 1983 pp.132–137
3. Instruction cache replacement policies and organizations;Smith J.E.;IEEE Trans. Comput.,1985
4. Quinones E. Berger E. Bernat G. et al.: ‘Using randomized caches in probabilistic real‐time systems’.21st Euromicro Conf. on Real‐Time Systems (ECRTS'09) Dublin Ireland July2009 pp.129–138
5. Kosmidis L. Abella J. Quinones E. et al.: ‘A cache design for probabilistically analysable real‐time systems’.Proc. Conf. on Design Automation and Test in Europe (DATE'13) Grenoble France 2013 pp.513–518
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