Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms-Reference-Cited by-同舟云学术

Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms

Published:2017-10-24 Issue:6 Volume:11 Page:221-230
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Zagan Ionel¹²,Găitan Vasile Gheorghiţă¹²

Affiliation:

1. Stefan cel Mare University of SuceavaSuceavaRomania

2. Integrated Center for Research, Development and Innovation in Advanced Materials, Nanotechnologies, and Distributed Systems for Fabrication and Control (MANSiD)Stefan cel Mare UniversitySuceavaRomania

Funder

European Regional Development Fund

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2017.0163

Reference26 articles.

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4. Zimmer M. Broman D. Shaver C. et al.: ‘FlexPRET: a processor platform for mixed‐criticality systems’.Proc. of the 20th IEEE Real‐Time and Embedded Technology and Application Symp. (RTAS) Berlin Germany 15–17 April2014 doi:10.1109/RTAS.2014.6925994

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