Yield‐driven design‐time task scheduling techniques for multi‐processor system on chips under process variation: a comparative study-Reference-Cited by-同舟云学术

Yield‐driven design‐time task scheduling techniques for multi‐processor system on chips under process variation: a comparative study

Published:2015-07 Issue:4 Volume:9 Page:221-229
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Momtazpour Mahmoud¹,Assare Omid²,Rahmati Negar³,Boroumand Amirali⁴,Barati Saeid⁵,Goudarzi Maziar⁶

Affiliation:

1. Electrical EngineeringSharif University of TechnologyTehranIran

2. University of California, San DiegoSan DiegoCaliforniaUSA

3. Stanford UniversitySanta ClaraCaliforniaUSA

4. Sharif University of TechnologyTehranIran

5. University of ChicagoChicagoIllinoisUSA

6. Department of Computer EngineeringSharif University of TechnologyTehranIran

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2014.0126

Reference30 articles.

1. Wang F. Nicopoulos C. Wu X. Xie Y. Vijaykrishnan N.: ‘Variation‐aware task allocation and scheduling for MPSoC’.IEEE/ACM Int. Conf. on Computer‐Aided Design (ICCAD'07) November2007 pp.598–603

2. Variation‐aware task and communication mapping for MPSoC architecture;Wang F.;IEEE Trans. Comput.‐Aided Des. Integr. Circuits Syst. (TCAD),2011

3. Singhal L. Oh S. Bozorgzadeh E.: ‘Yield maximization for system‐level task assignment and configuration selection of configurable multiprocessors’.Sixth IEEE/ACM/IFIP IntConf. on Hardware/Software Codesign and System Synthesis (CODES + ISSS'08) 2008 pp.249–254

4. Process‐variation aware mapping of best‐effort and real‐time streaming applications to MPSoCs;Mirzoyan D.;To Appear In: ACM Trans. Embed. Comput. Syst. (TECS),2013

5. Chon H. Kim T.: ‘Timing variation‐aware task scheduling and binding for MPSoC’.Asia and South Pacific Design Automation Conf. (ASPDAC'09) January2009 pp.137–142

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