System‐level assertions: approach for electronic system‐level verification

Author:

Sohofi Hassan1,Navabi Zainalabedin1

Affiliation:

1. School of Electrical and Computer EngineeringUniversity of TehranTehranIran

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference28 articles.

1. IEEE Standard SystemC Language Reference Manual IEEE Standard 1666‐2011 2011 DOI =http://www.accellera.org

2. International Technology Roadmap for Semiconductors (ITRS) – Design 2011 DOI =http://www.itrs.net/Links/2011ITRS/Home2011.htm

3. Accellera Standard OVL V2 Reference Manual Accellera Systems Initiative 2013

4. IEEE Standard for Property Specification Language (PSL) IEEE Standard 1850‐2010 2010

5. IEEE Standard for SystemVerilog: Unified Hardware Design Specification and Verification Language IEEE Standard 1800 2012

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