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Built‐in self test design of power switch with clock‐gated charge/discharge transistor

  • Published:2014-03 Issue:2 Volume:8 Page:59-69
  • ISSN:1751-8601
  • Container-title:IET Computers & Digital Techniques
  • language:en
  • Short-container-title:IET Computers & Digital Techniques

Author:

Xin Chen1,Ning Wu1,Na Bai2,Hui Huang1,Wei Hu1

Affiliation:

1. College of Electronic and Information EngineeringNanjing University of Aeronautics and AstronauticsNanjing210016JiangSuPeople's Republic of China

2. School of Electronics and Information EngineeringAnhui UniversityHeFei230601AnHuiPeople's Republic of China

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference12 articles.

1. Power‐gating noise minimization by three‐step wake‐up partitioning;Singh R.;IEEE Trans. Circuits Syst. I, Regul. Pap.,2012

2. Design of a tri‐modal multi‐threshold CMOS switch with application to data retentive power gating;Pakbaznia E.;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2012

3. Sleep mode analysis and optimization with minimal‐sized power gating switch for ultra‐low Vdd operation;Mingoo S.;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2012

4. Adaptive power control technique on power‐gated circuitries;Wei‐Chih H.;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2011

5. Design of a flexible reactivation cell for safe power‐mode transition in power‐gated circuits;Calimera A.;IEEE Trans. Circuits Syst. I, Regul. Pap.,2009
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