Two‐stage logarithmic converter with reduced memory requirements

Author:

Chaudhary Mandeep1,Lee Peter1

Affiliation:

1. School of Engineering and Digital ArtsUniversity of KentCanterburyKentUK

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference36 articles.

1. Sheikh F. Mathew S. Anders M. Hsu S. Agarwal A.: ‘A 2.05gvertices/S 151 mw lighting accelerator for 3d graphics vertex and pixel shading in 32 nm Cmos’.2012

2. The NVIDIA GeForce 8800 GPU

3. Melnikoff S.J. Quigley S.F. Russell M.J.: ‘Speech recognition on an FPGA using discrete and continuous hidden Markov models’.Proc. Reconfigurable Computing Is Going Mainstream 12th Int. Conf. on Field‐Programmable Logic and Applications Springer–Verlag 2002

4. Li H. Jullien G.A. Dimitrov V.S. Ahmadi M. Miller W.C.: ‘A 2‐digit multidimensional logarithmic number system filterbank for a digital hearing aid architecture’.IEEE Int. Symp. on Circuits and Systems 2002. ISCAS 2002. 2002

5. Arnold M.G.: ‘Reduced power consumption for mpeg decoding with LNS’.Proc. IEEE Int. Conf. on Application‐Specific Systems Architectures and Processors 2002 2002

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