Low‐cost security aware HLS methodology-Reference-Cited by-同舟云学术

Low‐cost security aware HLS methodology

Published:2017-01-10 Issue:2 Volume:11 Page:68-79
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Sengupta Anirban¹,Bhadauria Saumya¹,Mohanty Saraju P.²

Affiliation:

1. Computer Science and EngineeringIndian Institute of Technology IndoreIndoreIndia

2. Computer Science and EngineeringUniversity of North TexasDentonTXUSA

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2016.0014

Reference40 articles.

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4. Rajendran J. Zhang H. Sinanoglu O. et al.: ‘High‐level synthesis for security and trust’.Proc. of the IEEE 19th Int. On‐Line Testing Symp. (IOLTS) 2013 pp.232–233

5. Jin Y. Makris Y.: ‘Hardware Trojan detection using path delay fingerprint’.Proc. of the IEEE Symp. on Hardware‐Oriented Security and Trust 2008 pp.51–57

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1. Development of Multiobjective High-Level Synthesis for FPGAs;Scientific Programming;2020-06-29

2. Low Cost Functional Obfuscation of Reusable IP Cores Used in CE Hardware Through Robust Locking;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-04

3. Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware;IEEE Access;2019

4. Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters];IEEE Consumer Electronics Magazine;2017-07

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