Customised soft processor design: a compromise between architecture description languages and parameterisable processors

Author:

Vakili Shervin1,Langlois J.M. Pierre1,Bois Guy1

Affiliation:

1. Department of Computer EngineeringÉcole Polytechnique de MontréalMontrealCanada

Funder

Fonds Québécois de la Recherche sur la Nature et les Technologies

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference22 articles.

1. Embedded systems survey: Who uses custom chips;Turley J.;Embedded Syst. Program.,2005

2. Karuri K. Leupers R. Ascheid G. Meyr H.: ‘A generic design flow for application specific processor customization through instruction‐set extensions (ISEs)’.Proc. Int. Workshop on Embedded Computer Systems: Architectures Modeling and Simulation July2009 pp.204–214

3. Jain M.K. Balakrishnan M. Kumar A.: ‘ASIP design methodologies: survey and issues’.Proc. Int. Conf. VLSI Design January2001 pp.76–81

4. Exploration and customization of FPGA‐based soft processors;Yiannacouras P.;IEEE Trans. Comput.‐Aided Des. Integr. Circuits Syst.,2007

5. Architecture description languages for programmable embedded systems

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1. Real-Time Event Handling and Preemptive Hardware RTOS Scheduling on a Custom CPU Implementation;Canadian Journal of Electrical and Computer Engineering;2020

2. Hardware Scheduler Implementation based on Replicated Resource Architecture for Reconfigurable Systems;Proceedings of the 2019 3rd International Symposium on Computer Science and Intelligent Control;2019-09-25

3. Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors;Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems;2016-05-23

4. Accuracy‐aware processor customisation for fixed‐point arithmetic;IET Computers & Digital Techniques;2016-01

5. A proposed synthesis method for Application-Specific Instruction Set Processors;Microelectronics Journal;2015-03

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