High performance and predictable memory controller for multicore mixed‐criticality real‐time systems-Reference-Cited by-同舟云学术

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

Published:2019-07-16 Issue:5 Volume:13 Page:376-382
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Dabaghi Arezoo¹,Farbeh Hamed²³

Affiliation:

1. Department of Computer EngineeringSharif University of TechnologyTehranIran

2. Department of Computer EngineeringAmirkabir University of TechnologyTehranIran

3. School of Computer ScienceInstitute for Research in Fundamental Sciences (IPM)TehranIran

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.5031

Reference28 articles.

1. Makrani H.M. Monazzah A.M.H. Farbeh H. et al.: ‘Evaluation of software‐based fault‐tolerant techniques on embedded OS's components’.Proc Int. Conf. Depend. Lisbon Portugal November2014 pp.51–57

2. Farbeh H. Fazeli M. Khosravi F. et al.: ‘Memory mapped spm: protecting instruction scratchpad memory in embedded systems against soft errors’.Proc. Euro. Depend. Comput. Conf. Sibiu Romania May2012 pp.218–226

3. Sayadi H. Farbeh H. Monazzah A.M.H. et al.: ‘A data recomputation approach for reliability improvement of scratchpad memory in embedded systems’.Proc. Int. Symp. Defect and Fault Tolerance VLSI and Nanotechnology System Amsterdam Netherlands October2014 pp.228–233

4. Biondi A. Marinoni M. Buttazzo G. et al.: ‘Challenges in virtualizing safety‐critical cyber physical systems’.Proc. Int. Conf. Embedded World Nurnberg Germany February2018 pp.1–5

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