Cone-based placement for field programmable gate arrays
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2009.0058?crawler=true&mimetype=application/pdf
Reference23 articles.
1. Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs
2. Betz, V., and Rose, J.: ‘VPR: a new packing, placement and routing tool for FPGA research’, Luk, W., Cheung, P.Y., Glesner, M., Field-programmable logic and applications, (Springer-Verlag, Berlin, London, UK 1997 September), p. 213–222
3. Betz, V., Rose, J., and Marquardt, A.: ‘Architecture and CAD for deep-submicron FPGAs’, The Springer International Series in Engineering and Computer Science, 1st(Springer 1999 March, 31),497,
4. Timing-driven placement for FPGAs
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