Low‐power enhanced system‐on‐chip design for sequential minimal optimisation learning core with tri‐layer bus and butterfly‐path accelerator-Reference-Cited by-同舟云学术

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Low‐power enhanced system‐on‐chip design for sequential minimal optimisation learning core with tri‐layer bus and butterfly‐path accelerator

Published:2015-03 Issue:2 Volume:9 Page:93-100
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Peng Chih‐Hsiang¹,Lin Po‐Chuan²,Barma Shovan¹,Wang Jhing‐Fa¹,Peng Hong‐Yuan¹,Bharanitharan Karunanithi³,Kuan Ta‐Wen¹

Affiliation:

1. Department of Electrical EngineeringNational Cheng Kung UniversityTainan70101Taiwan

2. Department of Digital Game and Animation DesignMultimedia and Digital System Design LaboratoryTung‐Fang Design InstituteKaohsiung City82941Taiwan

3. Department of Electrical EngineeringFeng Chia UniversityTaichung40724Taiwan

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2013.0153

Reference29 articles.

1. Support-vector networks

2. Speaker verification using support vector machines and high‐level features;Campbell W.M.;IEEE Trans. Speech, Audio Lang. Process.,2007

3. Global convergence of SMO algorithm for support vector regression;Takahashi N.;IEEE Trans. Neural Netw.,2008

4. Wang J.‐F. Peng J.‐S. Wang J.‐C. et al.: ‘Hardware/software co‐design for fast‐trainable speaker identification system based on SMO’.Proc. IEEE Int. Conf. Systems Man and Cybernetics Anchorage AK October2011 pp.1621–1625

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1. VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability;IEEE Transactions on Biomedical Circuits and Systems;2018-02

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