Modelling and verification of program logic controllers using timed automata-Reference-Cited by-同舟云学术

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Modelling and verification of program logic controllers using timed automata

Published:2007-08-01 Issue:4 Volume:1 Page:127-131
ISSN:1751-8806
Container-title:IET Software
language:en
Short-container-title:

Author:

Wang R.,Gu M.,Song X.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computer Graphics and Computer-Aided Design

Link

https://digital-library.theiet.org/content/journals/10.1049/iet-sen_20070009?crawler=true&mimetype=application/pdf

Reference14 articles.

1. Clarke, E.M., and Grumberg, O.: ‘Model checking’, (The MIT Press 1999)

2. Towards the automatic verification of PLC programs written in Instruction List

3. ‘Compact timed automata for PLC program’, Technical Reprot, University of Nijmegen, 1999

4. http://www.uppaal.com, accessed January 2007

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1. Analysis of SpaceWire Link Initialization Time based on Timed Automata;2019

2. An overview of model checking practices on verification of PLC software;Software & Systems Modeling;2014-12-25

3. A Component-Based Modeling and Validation Method for PLC Systems;Advances in Mechanical Engineering;2014-01-01

4. Model Checking for SpaceWire Link Interface Design Using Uppaal;2013 IEEE 37th Annual Computer Software and Applications Conference Workshops;2013-07

5. Using Timed Automata for Modeling Distributed Systems with Clocks: Challenges and Solutions;IEEE Transactions on Software Engineering;2013-06

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