Design of a clock synchronisation sub-system for parallel embedded systems-Reference-Cited by-同舟云学术

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Design of a clock synchronisation sub-system for parallel embedded systems

Published:1997 Issue:2 Volume:144 Page:65
ISSN:1350-2387
Container-title:IEE Proceedings - Computers and Digital Techniques
language:en
Short-container-title:IEE Proc., Comput. Digit. Tech.

Author:

Fleury M.,Downton A.C.,Clark A.F.,Sava H.P.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science

Link

https://digital-library.theiet.org/content/journals/10.1049/ip-cdt_19971155?crawler=true&mimetype=application/pdf

Reference41 articles.

1. Edward, M.N.: ‘Radar signal processing on a fault tolerant transputer array’, Durrani, T.S., Sandham, W.A., Soraghan, J.J., Forbes, S.M., Applications of transputers 3, (IOS Amsterdam 1991)

2. Spoken language recognition on a DSP array processor

3. High speed video compression testbed

4. Coffin, M.H.: ‘Parallel programming a new approach’, (Silicon Press Summit NJ 1992), p. 149–155

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Distributed numerical controllers;SPIE Proceedings;2001-12-27

2. Pipelined parallelisation of automatic face inspection;Machine Vision and Applications;2000-12-01

3. Scheduling schemes for data farming;IEE Proceedings - Computers and Digital Techniques;1999

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