1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking

Author:

Wang C.-C.,Wu C.-F.,Tsai K.-C.

Publisher

Institution of Engineering and Technology (IET)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science

Cited by 33 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Efficient Dynamic Logic Magnitude Comparators;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

2. Modified priority encoder based hardware efficient N-bit comparator;International Journal of Electronics Letters;2022-09-02

3. Design of Energy Efficient Magnitude Comparator Architecture using 8T XOR Gate;2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC);2022-08-17

4. Low-Power and Fast-Swing-Restoration GDI-Based Magnitude Comparator for Digital Images Processing;Circuits, Systems, and Signal Processing;2022-05-30

5. SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits;International Journal of Circuit Theory and Applications;2022-02-16

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