An efficient implementation for linear convolution with reduced latency in FPGA

Abstract

AbstractA recently developed linear convolution filter based on Hirschman theory has shown its advantage in saving computations compared with other convolution filters. Here, the Hirschman convolution filter is improved with the use of the split‐radix algorithm and explore its latency‐reduced advantage for the first time. A comparison of hardware resources in Field Programmable Gate Array (FPGA) between the proposed Hirschman‐based filter and other convolution filters is presented. Simulation results indicate that the split‐radix Hirschman convolution filter achieves a promising reduction in latency by 18.15% on average with an acceptable power consumption rise by about 3.05%. In the case of a device capacity limited implementation, the proposed Hirschman convolution filter is still computationally attractive as it uses a small‐size originator function instead of larger Fourier transform.