Bulk linearisation of the MOS resistor
Author:
Affiliation:
1. Electrical Engineering DepartmentUniversidad Católica del UruguayMontevideoUruguay
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2018.5482
Reference4 articles.
1. CMOS transconductor with improved linearity using the bulk of self‐cascode transistors
2. Nanopower OTAs with improved linearity and low input offset using bulk degeneration;Gak J.;Trans. Circuits Syst. I, Reg. Pap.,2014
3. A precision pseudo resistor bias scheme for the design of very large time constant filters;Puddu R.;Trans. Circuits Syst. II, Express Briefs,2017
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1. Enhancing an OTA Linearity Through Bulk Degeneration: a Comparative Analysis;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27
2. A Power-Efficient Linearized Open-Loop OTA Utilizing Reconfigurable Tail-Resistor Pair;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08
3. A Bootstrapped Pseudo Resistor by Reusing OTA-C Filter for Neural Signal Processing;IEEE Transactions on Circuits and Systems II: Express Briefs;2021
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