Hybrid interconnect network for on‐chip low‐power clock distribution
Author:
Affiliation:
1. School of Electronics and Computer ScienceUniversity of SouthamptonSouthamptonUK
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2018.6570
Reference5 articles.
1. New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration
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4. Electromagnetic simulation modeling of silicon substrate for 60 GHz on‐chip differential‐feed dipole antenna;Hirano T.;Appl. Phys. Lett.,2013
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