Double random sources: low‐cost method to enhance local optima escaping ability in CMOS‐type Ising chips
Author:
Affiliation:
1. College of ComputerNational University of Defense TechnologyChangsha410073People's Republic of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2016.2218
Reference5 articles.
1. A 20k‐spin Ising chip to solve combinatorial optimization problems with CMOS annealing;Yamaoka M.;J. Solid‐State Circuit,2016
2. Uncertain behaviours of integrated circuits improve computational performance;Yoshimura C.;Sci. Rep.,2015
3. On greedy construction heuristics for the max‐cut problem;Kahruman S.;Int. J. Comput. Sci. Eng.,2007
4. COPhy Junior Research Group: ‘Spin Glass Server’ http://www.informatik.uni‐koeln.de/spinglass
5. Optimised simulated annealing for Ising spin glasses
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1. Universal Pre-Calculating Structure: Reducing Complexity of Ising Chips with Arbitrary Connectivity;2021 IEEE Sixth International Conference on Data Science in Cyberspace (DSC);2021-10
2. Advancing CMOS-Type Ising Arithmetic Unit into the Domain of Real-World Applications;IEEE Transactions on Computers;2018-05-01
3. Live Demonstration: Image Segmentation on the FPGA-based Pre-calculating Ising Memory;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05
4. Pre-Calculating Ising Memory: Low Cost Method to Enhance Traditional Memory with Ising Ability;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05
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