Affiliation:
1. School of Micro‐Nano Electronics Zhejiang University Hangzhou China
2. Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China
3. Polytechnic Institute Zhejiang University Hangzhou China
Abstract
AbstractIn this paper, a novel Resistive Random‐Access Memory (RRAM) read circuit has been designed and verified by simulation based on the RRAM model and parasitic capacitance of the circuit. Simulation results demonstrate the feasibility and effectiveness of the proposed circuit, with accurate reading of RRAM states and fast reading speed in the nanosecond range. The sense margin of the proposed circuit has improved as the array size increases, enhancing its application for advanced node RRAM array manufacture. Compared with conventional circuits, the proposed circuit achieved power consumption reduction of 6% and area reduction of 46.9 um2, resulting in a 97.5% reduction in area, providing an effective solution to address the cost and chip size challenges associated with RRAM industrialization.
Funder
National Natural Science Foundation of China
Natural Science Foundation of Zhejiang Province
China Association for Science and Technology
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering