Universal masking on logic gate level-Reference-Cited by-同舟云学术

Universal masking on logic gate level

Published:2004 Issue:9 Volume:40 Page:526
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. Lett.

Author:

Golić J.Dj.,Menicocci R.

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://digital-library.theiet.org/content/journals/10.1049/el_20040385?crawler=true&mimetype=application/pdf

Reference4 articles.

1. Differential Power Analysis

2. Messerges, T., Dabbish, E., and Puhl, L.: ‘Method and apparatus for preventing information leakage attacks on a microelectronic assembly’, (US Patent 6,295,606 B1)

3. DeKaRT: A New Paradigm for Key-Dependent Reversible Circuits

4. Menicocci, R., and Pascal, J.: ‘Elaborazione crittografica di dati digitali mascherati’, (Italian patent pending MI2003A001375)

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