Temperature dependence of drain-induced barrier lowering in deep submicrometre MOSFETs
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_19940577?crawler=true&mimetype=application/pdf
Reference6 articles.
1. A parametric short-channel MOS transistor model for subthreshold and strong inversion current
2. Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations
3. DIBL in short-channel NMOS devices at 77 K
4. Threshold voltage model for deep-submicrometer MOSFETs
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