Analysis of parasitic effects in triple‐well CMOS SPDT switch
Author:
Affiliation:
1. IBM2070 Rt 52Hopewell Jct.NY12533USA
2. Marvell SemiconductorSanta ClaraCA95054USA
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2013.0945
Reference6 articles.
1. 15-GHz fully integrated nMOS switches in a 0.13-/spl mu/m CMOS process
2. Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance
3. 16.6‐ and 28‐GHz fully integrated CMOS RF switches with improved body floating;Li Q.;IEEE Trans. Microw. Theory Tech.,2008
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2. 40 dB-Isolation, 1.85 dB-Insertion Loss Full CMOS SPDT Switch with Body-Floating Technique and Ultra-Small Active Matching Network Using On-Chip Solenoid Inductor for BLE Applications;Electronics;2018-11-05
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